Pulse width modulators are typically utilized to generate a pulse of a predetermined width. To accurately define width of a pulse, a clocked system is typically utilized wherein the clock frequency is divided by some type of counter such that a predetermined number of clock pulses can be counted with the rising and falling edge of the pulse defined in some manner by the edge of the clock. Another method for defining this pulse width is to utilize some type of RC circuit wherein a timing capacitor will define a pulse width due to the length of time it takes for the charge from a capacitor to decay from a predetermined level to a lower second predetermined level through a resistor.
When a counter is utilized, this counter typically must be a synchronous counter. One problem that exists with utilizing a counter is that the designer must ensure that the output of the counter is decoded in such a manner that there are no "false" edges. This could result from two transitions occurring simultaneously on the input to the decode circuitry, such that the pulse is prematurely brought low, and the duration thereof is inaccurate. This is due to the fact that the synchronous system synchronizes all transitions to the main clock.